TOP = cnet_reg_integrated_tb

SRCS = $(TOP).v cnet.v

SRC_DIR = ../../src
CNET_SRC_DIR = ../../../CNET/src
INC_DIR = ../../../common/src

SIMPRIMS = /cad/xilinx/ise9.1i/verilog/src/simprims
COREGENLIBS = /cad/xilinx/ise9.1i/verilog/src/XilinxCoreLib

DEFINES_SRCS = ../../../common/src/defines.v

VCS_FLAGS = +v2k +libext+.v -timescale=1ns/1ns

# DUMP_CTRL may be overidden by script calling this
DUMP_CTRL=

MODELSIM_CORELIB = /cad/xilinx/ise9.1i/XilinxLibs/XilinxCoreLib

# make sure we can build under VCS and ModelSim
# simv is generated by vcs
# top is not generated but will force ModelSim's vlog to be run
all: simv top

simv: $(SRCS) $(DEFINES_SRCS) $(DUMP_CTRL)
	vcs $(VCS_FLAGS) -y $(SRC_DIR) -y $(CNET_SRC_DIR) -y $(COREGENLIBS) -y $(SIMPRIMS) +incdir+$(INC_DIR) $(DEFINES_SRCS) $(SRCS) $(DUMP_CTRL)

# Once vlog has built, simulate with 
# % vsim -c -L /cad/xilinx/ise9.1i/XilinxLibs/XilinxCoreLib <top_module>
top: $(SRCS) $(DEFINES_SRCS) work
	vlog -incr $(DEFINES_SRCS) $(SRC_DIR)/*.v $(SRCS) $(DUMP_CTRL)
	@echo To simulate: vsim -c -L /cad/xilinx/ise9.1i/XilinxLibs/XilinxCoreLib $(TOP)

work: 
	vlib work

clean:
	rm -rf work simv transcript *~
